1. Field of the Invention
The present invention relates to a ramp wave generation circuit that generates a ramp wave having a voltage value which increases or decreases over time, and a solid-state imaging device including the ramp wave generation circuit.
This application claims the benefits of Japanese Patent Application No. 2011-208976, filed Sep. 26, 2011, the disclosure of which is hereby incorporated herein by reference in its entirety.
2. Description of Related Art
FIG. 20 illustrates an example of a configuration of a solid-state imaging device with an ADC (Analog-Digital converter) in each pixel column.
A solid-state imaging device 1 illustrated in FIG. 20 includes an imaging unit 2, a row scanning circuit 3, a column scanning circuit 4, a timing control circuit 5, an ADC group 6, a ramp wave generation circuit 7, a counter 8, and a data output circuit 9 including a sense amplifier circuit.
In the imaging unit 2, unit pixels 20 each including a photodiode and an in-pixel amplifier and outputting a pixel signal according to an amount of an incident electromagnetic wave are arranged in a matrix shape. The timing control circuit 5 is a control circuit for sequentially reading the pixel signals from the imaging unit 2. The row scanning circuit 3 performs control of a row address or row scanning of the imaging unit 2 via a row control line 21. The column scanning circuit 4 performs control of a column address or column scanning of the ADC group 6. The ramp wave generation circuit 7 generates a ramp wave having a voltage value which increases or decreases over time.
The ADC group 6 has an n-bit digital signal conversion function, and includes a column ADC unit 60 provided in a vertical signal line 22 corresponding to each pixel column. The column ADC unit 60 includes a comparator 601 and a latch unit 602. The comparator 601 compares the ramp wave generated by the ramp wave generation circuit 7 with an analog signal obtained from the unit pixel 20 via each vertical signal line 22 for each row control line 21. The latch unit 602 includes latch circuits 603 and 604 that hold a counting result of the counter 8, which counts a comparison time. An output of each latch unit 602 is connected to a horizontal transfer line 117 having a 2n-bit width. The data output circuit 9 includes 2n sense circuits corresponding to the respective horizontal transfer lines 117.
Next, an operation of the solid-state imaging device 1 will be described. From each unit pixel 20 on a selected row of the imaging unit 2, as an analog pixel signal, a reset level containing noise of a pixel signal is read in a first reading operation and then a signal level is read in a second reading operation. Also, the reset level and the signal level are input to the ADC group 6 via the vertical signal line 22 in chronological order.
After first reading from the unit pixel 20 of any row to the vertical signal line 22 is stabilized, a ramp wave obtained by changing a reference voltage in terms of time is generated by the ramp wave generation circuit 7 and is input to the comparator 601. The comparator 601 compares the voltage of any vertical signal line 22 with the ramp wave. First counting is performed by the counter 8 when the ramp wave is input to the comparator 601.
When the voltage level of the ramp wave and the voltage of any vertical signal line 22 become the same, the output of the comparator 601 is inverted, and simultaneously a count value corresponding to the comparison period is held in the latch unit 602. In the first reading, since variation in the reset level of the unit pixel 20 is generally small and the reset voltage is common to all pixels, the output of any vertical signal line 22 is substantially the same as a known value. Accordingly, in a first reading of the reset level, the comparison period may be shortened by appropriately adjusting the voltage of the ramp wave.
In second reading, a signal level corresponding to an incident light amount of each unit pixel 20 is read in addition to the reset level, and an operation similar to the first reading is performed. In other words, after second reading from the unit pixel 20 of any row to any vertical signal line 22 is stabilized, the ramp wave obtained by changing a reference voltage in terms of time is generated by the ramp wave generation circuit 7 and is input to the comparator 601.
The comparator 601 compares the voltage of any vertical signal line 22 with the ramp wave. Second counting is performed by the counter 8 when the ramp wave is input to the comparator 601.
When the voltage level of the ramp wave and the voltage of any vertical signal line 22 become the same, an output of the comparator 601 is inverted and simultaneously a count value corresponding to the comparison period is held in the latch unit 602. A first count value is held, for example, in the latch circuit 603, and a second count value is held, for example, in the latch circuit 604.
After the two reading operations end, the first and second n-bit digital signals held in the latch unit 602 are detected by the data output circuit 9 via the 2n horizontal transfer lines 117 according to the column scanning circuit 4. Then, in a subtraction circuit, the signal obtained in the first reading is sequentially subtracted from the signal obtained in the second reading, and then a resultant signal is output to the outside. Then, sequentially, a similar operation is repeatedly performed for the respective rows to generate a two-dimensional image.
A scanning circuit that can be applied to a solid-state imaging device is described in Japanese Unexamined Patent Application, First Publication No. 2002-158933.